ADT7463
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23
SMBALERT
 Interrupt Behavior
The ADT7463 can be polled for status, or an SMBALERT
interrupt can be generated for outoflimit conditions. It is
important to note how the SMBALERT
 output and status
bits behave when writing Interrupt Handler software.
Figure 34. SMBALERT
 and Status Bit Behavior
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
Figure 34 shows how the SMBALERT
  output and
sticky status bits behave. Once a limit is exceeded, the
corresponding status bit gets set to 1. The status bit remains
set until the error condition subsides and the status register
gets read. The status bits are referred to as sticky since they
remain set until read by software. This ensures that an
outoflimit event cannot be missed if software is polling
the device periodically. Note that the SMBALERT
 output
remains low for the entire duration that a reading is
outoflimit and until the status register has been read. This
has implications on how software handles the interrupt.
Handling SMBALERT
 Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommend to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT
 assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
Figure 35. How Masking the Interrupt Source Affects
SMBALERT
 Output
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT
 REARMED)
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(Reg. 0x74, 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the Interrupt Handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0.
This causes the SMBALERT
 output and status bits
to behave as shown in Figure 35.
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses
0x74 and 0x75. These allow individual interrupt sources to
be masked out to prevent SMBALERT
 interrupts. Note that
masking an interrupt source only prevents the SMBALERT
output from being asserted; the appropriate status bit gets set
as normal.
Table 29. INTERRUPT MASK REGISTER 1
(REG. 0X74)
Bit
Mnemonic
Description
7
OOL
1 masks SMBALERT
 for any alert
condition flagged in Status Register 2.
6
R2T
1 masks SMBALERT
 for Remote 2
temperature.
5
LT
1 masks SMBALERT
 for Local
Temperature.
4
R1T
1 masks SMBALERT
 for Remote 1
Temperature.
3
5V
1 masks SMBALERT
 for 5 V channel.
2
V
CC
1 masks SMBALERT
 for V
CC
 channel.
1
V
CCP
1 masks SMBALERT
 for V
CCP
 channel.
0
2.5V
1 masks SMBALERT
 for 2.5 V channel.
Table 30. INTERRUPT MASK REGISTER 2
(REG. 0X75)
Bit
Mnemonic
Description
7
D2
1 masks SMBALERT
 for Diode 2 errors.
6
D1
1 masks SMBALERT
 for Diode 1 errors.
5
FAN4
1 masks SMBALERT
 for Fan 4 failure. If
the TACH4 pin is being used as the
THERM
 input, this bit masks
SMBALERT
 for a THERM
 event.
4
FAN3
1 masks SMBALERT
 for Fan 3.
3
FAN2
1 masks SMBALERT
 for Fan 2.
2
FAN1
1 masks SMBALERT
 for Fan 1.
1
OVT
1 masks SMBALERT
 for
overtemperature (exceeding THERM
limits).
0
12V/VC
1 masks SMBALERT
 for 12 V channel
or for a VID code change, depending on
the function used.
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